The aim of integrating more and more functionality in a single integrated circuit (IC) has resulted in a fast and inevitable increase in System-on-Chip (SoC) design complexity. In this scenario, reuse-based design using hardware Intellectual Property (IP) cores has become extremely common. These IP cores are usually in the form of synthesizable Register-Transfer Level (RTL) descriptions in Hardware Description Languages (HDLs), or gate-level designs directly implementable in hardware. This approach of designing complex systems by integrating tested and verified, smaller and reusable modules can help reduce the design cycle time dramatically. It is quite common to have SoC designs where multiple IPs from different IP vendors are integrated by the chip designer and ultimately multiple such chips are integrated by the system designer to build the desired system. Unfortunately, recent trends in IP-piracy and reverse-engineering efforts to produce counterfeit ICs have raised serious concerns in the IC design community.